1. Field
Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a data output path of a semiconductor memory device.
2. Description of the Related Art
FIG. 1 illustrates a data output path of a conventional semiconductor memory device.
Referring to FIG. 1, the data output path 100 of a conventional semiconductor memory device includes a clock generator 110, a pipe latch 120, a pipe latch driver 130, a trigger 140, a pre-driver 150, and an output buffer 160. The clock generator 110 generates differential internal clocks RCLKDO, RCLKDOB, FCLKDO, and FCLKDOB in response to delay locked loop clocks RCLKDLL and FCLKDLL that are generated in a delay locked loop (DLL) (not shown). The pipe latch 120 serially outputs serial data RDOB and FDOB based on inputted data DATA in parallel in synchronization with falling and rising edges of a source clock. The pipe latch driver 130 drives the serial data RDOB and FDOB to output data RDODB and FDODB. The trigger 140 receives the data RDODB and FDODB and outputs a data UPDNB in synchronization with the differential internal clocks RCLKDO, RCLKDOB, FCLKDO, and FCLKDOB in response to an DDT bar signal ODTB and a DQS preamble fixing signal QPRE. The pre-driver 150 controls slew rate of the data UPDNB to output data RDATA and FDATA. The output buffer 160 receives the data RDATA and FDATA from the pre-driver 150 and outputs them to a data pad DQ.
FIG. 2 is a block diagram illustrating an internal structure of the clock generator 110 shown in FIG. 1.
Referring to FIG. 2, the clock generator 110 includes an inverter chain which includes inverters IV00, IV01, IV02, and IV03, and an inverter chain which includes inverters IV00′, IV01′, IV02′, and IV03′. The clock generator 110 receives the delay locked loop clock RCLKDLL and FCLKDLL and outputs the differential internal clocks RCLKDO, RCLKDOB, FCLKDO, and FCLKDOB. Herein, the differential internal clocks RCLKDO, RCLKDOB, FCLKDO, and FCLKDOB include differential internal clocks RCLKDO and RCLKDOB that are synchronized with a rising edge of the delay locked loop clock RCLKDLL, and differential internal clocks FCLKDO and FCLKDOB that are synchronized with a rising edge of the delay locked loop clock FCLKDLL.
FIG. 3 is a block diagram illustrating an internal structure of the pipe latch driver 130 shown in FIG. 1.
Referring to FIG. 3, the pipe latch driver 130 includes a first driving unit 131 and a second driving unit 133. The first driving unit 131 drives and outputs the data RDOB synchronized with the rising edge of the source clock. The second driving unit 133 drives and outputs the data FDOB synchronized with the falling edge of the source clock.
Herein, the first driving unit 131 includes a first PMOS transistor PP00, a second PMOS transistor PP01, a first NMOS transistor NN00, a second NMOS transistor NN01, and a first inverter IV04. The first PMOS transistor PP00 receives a ground voltage VSS through a gate, and includes a source and a drain coupled between a power source voltage (VDD) terminal and a first coupling node N00. The second PMOS transistor PP01 receives the data RDOB synchronized with the rising edge of the source clock through a gate, and includes a source and a drain coupled between the first coupling node N00 and a first output node ON00. The first NMOS transistor NN00 receives the data RDOB synchronized with the rising edge of the source clock through a gate, and includes a source and a drain coupled between the first output node ON00 and a second coupling node N01. The second NMOS transistor NN01 receives a power source voltage VDD through a gate, and includes a drain and a source coupled between the second coupling node N01 and a ground voltage (VSS) terminal. The first inverter IV04 inverts the output of the first output node ON00 and outputs an inverted output.
The second driving unit 133 has the same structure as the first driving unit 131, except that the data FDOB synchronized with the falling edge of the source clock is received. Thus, for the sake of convenience, further description on the second driving unit 133 is omitted herein.
FIG. 4 is a block diagram illustrating an internal structure of the trigger 140 shown in FIG. 1.
Referring to FIG. 4, the trigger 140 includes a first synchronization unit 141, a second synchronization unit 143, a first voltage level fixing unit 145, a second voltage level fixing unit 147, and an inversion unit 149.
The first synchronization unit 141 synchronizes the data RDODB in synchronization with the differential internal clocks RCLKDO and RCLKDOB and outputs a resultant signal to the second output node ON01. As described above, the data RDODB is synchronized with the rising edge of the source clock and received from the pipe latch driver 130. The differential internal clocks RCLKDO and RCLKDOB are synchronized with a rising edge of the delay locked loop clock RCLKDLL at the clock generator 110. The second synchronization unit 143 synchronizes the data FDODB in synchronization with the differential internal clocks FCLKDO and FCLKDOB and outputs a resultant signal to the second output node ON01. As described above, the data FDODB is synchronized with the falling edge of the source clock and received from the pipe latch driver 130. The differential internal clocks FCLKDO and FCLKDOB are synchronized with a falling edge of the delay locked loop clock FCLKDLL at the clock generator 110. The first voltage level fixing unit 145 fixes the second output node ON01 to the level of the power source voltage VDD in response to the ODT bar signal ODTB. The second voltage level fixing unit 147 fixes the second output node ON01 to the level of the ground voltage VSS in response to the DQS preamble fixing signal QPRE. The inversion unit 149 is coupled with the second output node ON01 and output a data UPDNB synchronized with the delay locked loop clocks RCLKDLL and FCLKDLL.
Herein, the first synchronization unit 141 includes a third PMOS transistor PP02, a fourth PMOS transistor PP03, a third NMOS transistor NN02, and a fourth NMOS transistor NN03. The third PMOS transistor PP02 receives an inverted differential internal clock RCLKDOB between the differential internal clocks RCLKDO and RCLKDOB that are synchronized with the rising edge of the delay locked loop clock RCLKDLL through a gate, and includes a source and a drain coupled between the power source voltage (VDD) terminal and a third coupling node N02. The fourth PMOS transistor PP03 receives a data RDODB, which is received from the pipe latch driver 130 and synchronized with the rising edge of the source clock, through a gate, and includes a source and a drain coupled between the third coupling node N02 and a second output node ON01. The third NMOS transistor NN02 receives the data RDODB, which is received from the pipe latch driver 130 and synchronized with the rising edge of the source clock, through a gate, and includes a drain and a source coupled between the second output node ON01 and a fourth coupling node N03. The fourth NMOS transistor NN03 receives an uninverted differential internal clock RCLKDO between the differential internal clocks RCLKDO and RCLKDOB that are synchronized with the rising edge of the delay locked loop clock RCLKDLL through a gate, and includes a drain and a source coupled between the fourth coupling node N03 and the ground voltage (VSS) terminal.
The second synchronization unit 143 includes a fifth PMOS transistor PP04, a sixth PMOS transistor PP05, a fifth NMOS transistor NN04, and a sixth NMOS transistor NN05. The fifth PMOS transistor PP04 receives an inverted differential internal clock FCLKDOB between the differential internal clocks FCLKDO and FCLKDOB that are synchronized with the falling edge of the delay locked loop clock FCLKDLL through a gate, and includes a source and a drain coupled between the power source voltage (VDD) terminal and a fifth coupling node N04. The sixth PMOS transistor PP05 receives a data FDODB, which is received from the pipe latch driver 130 and synchronized with the falling edge of the source clock, through a gate, and includes a source and a drain coupled between the fifth coupling node N04 and the second output node ON01. The fifth NMOS transistor NN04 receives the data FDODB, which is received from the pipe latch driver 130 and synchronized with the falling edge of the source clock, through a gate, and includes a drain and a source coupled between the second output node ON01 and a fifth coupling node N04. The sixth NMOS transistor NN05 receives an uninverted differential internal clock FCLKDO between the differential internal clocks FCLKDO and FCLKDOB that are synchronized with the falling edge of the delay locked loop clock FCLKDLL through a gate, and includes a drain and a source coupled between the sixth coupling node N05 and the ground voltage (VSS) terminal.
Also, the first voltage level fixing unit 145 includes a seventh PMOS transistor PP06 which receives the ODT bar signal ODTB through a gate, and includes a source and a drain coupled between the power source voltage (VDD) terminal and the second output node ON01. The seventh PMOS transistor PP06 receives the DQS preamble fixing signal QPRE through a gate and includes a source and a drain coupled between the ground voltage (VSS) terminal and the second output node ON01.
Hereinafter, an operation of the semiconductor memory device 100 in accordance with the above structure will be described.
When a data is read from a memory cell region (not shown in the drawings) upon a read operation, the pipe latch 120 converts the data DATA inputted in parallel into the serial data RDOB and FDOB and outputs the serial data RDOB and FDOB to the pipe latch driver 130. The pipe latch driver 130 drives the serial data RDOB and FDOB to output the data RDODB and FDODB to the trigger 140. The trigger 140 synchronizes the data RDODB and FDODB outputted from the pipe latch driver 130 with the differential internal clocks RCLKDO, RCLKDOB, FCLKDO, and FCLKDOB and outputs the data UPDNB to the pre-driver 150. The pre-driver 150 controls the slew rate of the data UPDNB outputted from the trigger 140 and outputs the data RDATA and FDATA to the output buffer 160. The output buffer 160 receives the data RDATA and FDATA and outputs them to the data pad DQ. As a result, the data outputted from the data pad DQ may be synchronized with a system clock so as to perform a stable read operation.
Meanwhile, when the semiconductor memory device enters an On Die Termination (ODT) mode, the ODT bar signal ODTB is enabled to a logic low level and the output UPDNB terminal of the trigger 140 is set to a logic low level. Then, any one between a structure for a pull-up operation and a structure for a pull-down operation operates among the circuit elements included in the pre-driver 150 and the output buffer 160, and the pre-driver 150 and the output buffer 160 are used as an ODT unit.
Also, when the DQS preamble fixing signal QPRE has a preamble period of a data strobe signal (DQS) as an enable period and is enabled to a logic high level during a read operation, the output UPDNB terminal of the trigger 140 is set to a logic high level. Then, as the output of the output buffer 160 is finally set to a predetermined voltage level, e.g., a logic high level, it indicates that the period is a preamble period of the data strobe signal (DQS).
However, the semiconductor memory device 100 having the above structure may have the following concerns.
The trigger 140 performs diverse operation according to a predetermined control signals such as the DQS preamble fixing signal QPRE and the ODT bar signal ODTB, other than an operation of transferring the data RDODB and FDODB that are outputted from the pipe latch driver 130. In short, the semiconductor memory device 100 enables the ODT unit by controlling the output terminal of the trigger 140 or represents that the period is the preamble period of the data strobe signal (DQS), while transferring data through the trigger 140. To this end, the trigger 140 includes the first voltage level fixing unit 145 and the second voltage level fixing unit 147, and the first voltage level fixing unit 145 and the second voltage level fixing unit 147 are implemented by using, for example, transistors. Therefore, the output UPDNB terminal of the trigger 140 has a deteriorated duty and jitter due to the coupling loading of the transistors.
Moreover, the transistors included in the first voltage level fixing unit 145 and the second voltage level fixing unit 147 may be desirable to have a size of greater than a predetermined size. As the size of the transistor is increased, the coupling load of the transistors is increased and duty characteristics may be deteriorated. Herein, since an enable period of the ODT unit and the preamble period of the data strobe signal (DQS) are decided according to specification and the output UPDNB of the trigger 140 should be driven up to a predetermined voltage level within a predetermined time, the transistors may be desirable to have a size of greater than a predetermined size. Meanwhile, since the trigger 140 basically outputs the data UPDNB in synchronization with the delay locked loop clocks RCLKDLL and FCLKDLL that are generated in a delay locked loop (not shown), it may be difficult to correct the duty of the data UPDNB outputted from the trigger 140.
As the first voltage level fixing unit 145 and the second voltage level fixing unit 147 are coupled with the second output node ON01 of the trigger 140, the output UPDNB of the trigger 140 may have a deteriorated duty characteristics. Furthermore, as the sizes of the transistors included in the first voltage level fixing unit 145 and the second voltage level fixing unit 147 may be increased and the duty characteristic may be more deteriorated, the semiconductor memory device 100 may some concerns in that operation reliability and stability are not secured in a high frequency and low power source voltage VDD.